Electronic Design Automation
Assembly Line
CELUS and Blues Partner to Drive Next-Generation Electronic Design
CELUS, a pioneer in AI-driven electronics design, has partnered with Blues, a leader in embedded intelligence, to simplify the design process for engineers. The partnership enables seamless integration of Blues’ Notecard products, which provide wireless connectivity and secure “off the internet” communication, into the CELUS Design Platform. This integration reduces development time and costs, while enhancing functionality and connectivity. The CELUS Design Platform uses AI-driven automation to evaluate over 600 million components, providing guided suggestions to designers and shortening the time it takes to bring new projects to market. The partnership also includes joint marketing efforts, driving a seamless experience for end-users and reinforcing both companies’ commitment to innovation and customer value. By combining CELUS’ design platform with Blues’ IoT connectivity, engineers and designers can now access production-ready embeddable communication modules, enabling better integration and improved innovation.
AutoDMP Finds Efficient Ways To Place Transistors On Silicon Chips
Macro placement is a critical very large-scale integration (VLSI) physical design problem that significantly impacts the design powerperformance-area (PPA) metrics. This paper proposes AutoDMP, a methodology that leverages DREAMPlace, a GPU-accelerated placer, to place macros and standard cells concurrently in conjunction with automated parameter tuning using a multi-objective hyperparameter optimization technique. As a result, we can generate high-quality predictable solutions, improving the macro placement quality of academic benchmarks compared to baseline results generated from academic and commercial tools. AutoDMP is also computationally efficient, optimizing a design with 2.7 million cells and 320 macros in 3 hours on a single NVIDIA DGX Station A100. This work demonstrates the promise and potential of combining GPU-accelerated algorithms and ML techniques for VLSI design automation
Designing in the Age of AI
Synopsys helps semiconductor designers accelerate chip design and development on Google Cloud
EDA software is a large consumer of high performance computing capacity in the cloud. With the release of Synopsys Cloud bring-your-own-cloud (BYOC) solution on Google Cloud, chip designers can now scale their Google Cloud infrastructure with Synopsys’s leading EDA tools under the flexible FlexEDA pay-per-use model and access unlimited EDA software license availability on-demand by the hour or minute.
Designing Billions of Circuits with Code
Bringing EDA to silicon helped solve daunting challenges in chip making. A chip is built in layers. Now you have to wire connections in 3-D, taking into consideration layer-to-layer connections called vias.