yieldWerx
Assembly Line
Ultimate Guide to Outlier Detection Using Part Average Testing
Part Average Testing (PAT) is a powerful outlier detection method that screens each die and sets limits across multiple test parameters. Static PAT (SPAT) sets clear boundaries to catch outliers, using a predefined set of tests and population data from multiple batches. These boundaries—called the lower and upper specification limits (LSL and USL)—act as a guardrail for screening dice that fall outside acceptable ranges. Updated every six months or after eight wafer lots (whichever comes first), SPAT calculates the mean (µ) and standard deviation (σ), setting limits at µ ± 6σ to ensure only quality parts move forward. SPAT can lead to excessively wide distributions compared to batch-by-batch estimates. Instead, Dynamic PAT (DPAT) takes a real-time approach, setting limits individually for each wafer test by calculating the mean and standard deviation for a specific lot. These limits are based on the actual material in front of you, eliminating lot-to-lot variation concerns. According to a KeySight case study, implementing pseudo-real-time Dynamic PAT limits instead of the per lot Static PAT limits process led to a reduction of greater than 2% in the total false rejects, a reduction of unnecessary scrap, a reduction of device handling, and improved equipment throughput due to the lower retest rate.